In general, an active-matrix type liquid crystal display device includes a liquid crystal panel formed of two substrates that sandwich a liquid crystal layer in between. On one of the two substrates, there are arranged in a lattice shape a plurality of gate bus lines (scanning signal lines) and a plurality of source bus lines (video signal lines). Further, a plurality of pixel formation portions arranged in a matrix shape are provided respectively corresponding to intersections between the plurality of gate bus lines and the plurality of source bus lines. Each pixel formation portion includes a thin film transistor (TFT) as a switching element having a gate terminal connected to a gate bus line that passes through a corresponding intersection and a source terminal connected to a source bus line that passes through the intersection, and a pixel capacitor for holding a pixel value. Further, on the other substrate out of the two substrates, there is provided in some cases a common electrode as a counter electrode that is provided common to the plurality of pixel formation portions. In the active-matrix type liquid crystal display device, there are further provided a gate driver (a scanning signal line drive circuit) for driving the plurality of gate bus lines and a source driver (a video signal line drive circuit) for driving the plurality of source bus lines.
While a video signal that indicates a pixel value is transmitted by the source bus lines, each source bus line cannot transmit at one time (simultaneously) video signals that indicate pixel values of a plurality of rows. Therefore, writing of a video signal to a pixel capacitor in the pixel formation portions arranged in the matrix shape is sequentially performed for each one row. Therefore, the gate driver is configured by a shift register formed of a plurality of stages so that a plurality of gate bus lines are sequentially selected by predetermined periods.
In such a liquid crystal display device, there is a case that even after a user turned off a power supply, a display is not cleared immediately and an image like a residual image remains. This is because when the power supply of a device is turned off, a discharge path of a charge held in the pixel capacitor is cut off, and a residual charge is accumulated in the pixel formation portion. When the power supply of the device is turned on in a state that a residual charge is accumulated in the pixel formation portion, reduction of a display quality, such as occurrence of flicker due to bias of impurities based on the residual charge, occurs. Accordingly, when the power supply is turned off, for example, all gate bus lines are set in a selected state (ON state) and a black voltage is applied to the source bus line, so that the charge on the panel is discharged.
Further, concerning the liquid crystal display device, a gate driver that is made monolithic is progressed in recent years. Conventionally, in many cases, gate drivers have been mounted as an IC (Integrated Circuit) chip, on a peripheral portion of a substrate that configures a liquid crystal panel. However, in recent years, the gate drivers have gradually come to be directly formed on the substrate. Such a gate driver is called a “monolithic gate driver”. Further, a panel that includes the monolithic gate driver is called a “gate driver monolithic panel”.
In the gate driver monolithic panel, the above method cannot be adopted concerning the discharge of a charge on the panel. In WO 2011/055584, the invention of the following liquid crystal display device is disclosed. In a bistable circuit that configures a shift register in a gate driver, there is provided a thin film transistor that has a drain terminal connected to a gate bus line, a source terminal connected to a reference potential wiring that transmits a reference potential, and a gate terminal that is applied with a clock signal for operating the shift register. In such a configuration, when supply of a power supply voltage from outside is cut off, the thin film transistor is set in the ON state by setting a clock signal to a high level, and also, a level of the reference potential is increased from a gate-off potential to a gate-on potential. Accordingly, a potential of each gate bus line is increased to the gate-on potential, and a residual charge in all pixel formation portions is discharged.